1 of 10 041305 features holds microprocessor in check during power transients automatically restarts microprocessor after power failure monitors pushbutton for external override accurate 5%, 10% or 20% resets for 3.3v systems and 5% or 10% resets for 5.0v systems eliminates the need for discrete components 20% tolerance compatible with 3.0v systems pin compatible with the maxim max707/max708 in 8-pin dip, 8-pin soic packages 8-pin dip, 8-pin and -sop soic and 8-pin -sop packages available industrial temperature range -40 c to +85 c pin assignment see mech. drawings section on website ds1707 and ds1708_r/s/t pin description pbrst - pushbutton reset input v cc - power supply gnd - ground in - input nmi - non-maskable interrupt nc - no connect rst - active low reset output rst - active high reset output description the ds1707/ds1708 3.3- or 5.0-volt microm onitor monitors three vital conditions for a microprocessor: power supply, voltage sense, and external override . a precision temperature-compensated reference and comparator circuit monitor the status of v cc at the device and at an upstream point for maximum protection. when the sense input detects an out- of-tolerance condition a non-maskable interrupt is generated. as the voltage at the device degrades an internal power fail signal is generated which forces the reset to an active state. when v cc returns to an in-tolerance conditi on, the reset signal is kept in the active state for a minimum of 130 ms to allow the power supply and processor to stabilize. ds1707/ds1708 3.3 and 5.0- v olt micromonito r www.maxim-ic.com 8-pin dip (300-mil) pbrst v cc gnd in rst rst nc nmi 12 3 4 87 6 5 8-pin -sop (118-mil) rst rst pbrst v cc nc nmi in gnd 12 3 4 87 6 5 8-pin soic (150-mil) 12 3 4 87 6 5 pbrst v cc gnd in rst rst nc nmi downloaded from: http:///
ds1707/ds1708 2 of 10 the third function the ds1707/ds1708 performs is pushbutton reset control. the ds1707/ds1708 debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum. operation power monitor the ds1707/ds1708 detects out-of-tole rance power supply conditions and warns a processor-based system of impending power failure. when v cc falls below the minimum v cc tolerance, a comparator outputs the rst and rst signals. rst and rst are excellent control signals for a microprocessor, as processing is stopped at the la st possible moment of valid v cc . on power-up, rst and rst are kept active for a minimum of 130 ms to allow the power supply and processor to stabilize. pushbutton reset the ds1707/ds1708 provides an input pi n for direct connection to a pus hbutton reset (see figure 2). the pushbutton reset input requires an ac tive low signal. internally, this input is debounced and timed such that rst and rst signals of at least 130 ms minimum will be generated. the 130 ms delay commences as the pushbutton reset input is released from the low level. the pushbutton can be initiated by connecting the nmi output to the pbrst input as shown in figure 3. non-maskable interrupt the ds1707/ds1708 generates a non-maskable interrupt ( nmi ) for early warning of a power failure. a precision comparator monitors the voltage level at the in pin relative to an on-chip reference generated by an internal band gap. the in pin is a high impedance input allowing for a user-defined sense point. an external resistor voltage divider network (figure 5) is used to interface with high voltage signals. this sense point may be derived from a regulated supply or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 1.25 volts, the proper values for r1 and r2 can be determined by the equation as shown in figure 5. proper operation of th e ds1707/ds1708 requires that the voltage at the in pin be limited to v cc . therefore, the maximum allowa ble voltage at the supply being monitored (v max ) can also be derived as shown in figure 5. a simple approach to solving the equation is to select a value for r2 high enough to keep power consumption low, and solve for r1. the flexibility of the in input pin allows for detection of power lo ss at the earliest point in a power supply system, maximizing the amount of time for system shut-down between nmi and rst/ rst . when the supply being monitored decays to th e voltage sense point, the ds1707/ds1708 pulses the nmi output to the active state for a minimum 200 s. the nmi power-fail detection circuitry also has built-in hysteresis of 100 v. the supply must be below the volta ge sense point for approximately 5 s before a low nmi will be generated. in this way, power supply noise is removed from the monitoring function, preventing false interrupts. during a powe r-up, any detected in pin levels below v tp by the comparator are disabled from generating an interrupt until v cc rises to v cctp . as a result, any potential nmi pulse will not be initiated until v cc reaches v cctp . connecting nmi to pbrst would allow the non-maskable interrupt to generate an automatic reset when an out-of-tolerance condition occurred in a monitored supply. an example is shown in figure 3. downloaded from: http:///
ds1707/ds1708 3 of 10 micromonitor block diagram figure 1 40k pushbutton reset figure 2 pushbutton reset controlled by nmi figure 3 downloaded from: http:///
ds1707/ds1708 4 of 10 timing diagram: pushbutton reset figure 4 non-maskable interrupt circuit example figure 5 v sense = r2 r2 r1 x 1.25 v max = tp sense v v x v cc example: v sense = 4.50v at the trip point v cc = 3.3v 1 0 k ? = r2 therefore: 25.1 50.4 x 3.3 = 11.88v maximum 4.50 = 10 k 10k r1 x 1.25 r1 = 26 k ? downloaded from: http:///
ds1707/ds1708 5 of 10 timing diagram: non-maskable interrupt figure 6 timing diagram: power-down figure 7 downloaded from: http:///
ds1707/ds1708 6 of 10 timing diagram: power up figure 8 downloaded from: http:///
ds1707/ds1708 7 of 10 absolute maximum ratings* voltage on v cc pin relative to ground -0.5v to +7.0v voltage on i/o relative to ground** -0.5v to v cc + 0.5v operating temperature -40 c to +85 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ** the voltage input limits on in and pbrst can be exceeded if the input current is less than 10 ma. recommended dc operating conditions (-40 c to +85 c) parameter symbol min typ max units notes supply voltage v cc 1.2 5.5 v 1 pbrst input high level v ih 2.0 v cc -0.5 v cc +0.3 v 1, 3 1, 4 pbrst input low level v il -0.03 +0.5 v 1 dc electrical characteristics (-40 c to +85 c; v cc =1.2v to 5.5v) parameter symbol min typ max units notes v cc trip point ds1707 v cctp 4.50 4.65 4.75 v 1 v cc trip point ds1708 v cctp 4.25 4.40 4.50 v 1 v cc trip point ds1708t v cctp 3.00 3.08 3.15 v 1 v cc trip point ds1708s v cctp 2.85 2.93 3.00 v 1 v cc trip point ds1708r v cctp 2.55 2.63 2.70 v 1 input leakage i il -1.0 +1.0 a 2 output current @ 2.4v i oh 350 a 3 output current @ 0.4v i ol 10 ma 3 output voltage @ -500a v oh v cc -0.3 v cc -0.1 v 3 operating current @ v cc < 5.5v i cc 60 a 5 operating current @ v cc < 3.6v i cc 50 a 5 in input trip point v tp 1.20 1.25 1.30 v 1 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf downloaded from: http:///
ds1707/ds1708 8 of 10 ac electrical characteristics (-40 c to +85 c; v cc =1.2v to 5.5v) parameter symbol min typ max units notes pbrst = v il t pb 150 ns reset active time t rst 130 205 285 ms v cc detect to rst and rst t rpd 5 8 s 7 v cc slew rate t f 20 s v cc detect to rst and rst t rpu 130 205 285 ms 6 v cc slew rate t r 0 ns pbrst stable low to rst and rst t pdly 250 ns vin detect to nmi t ipd 5 8 s 7 notes: 1. all voltages are referenced to ground. 2. pbrst is internally pulled up to v cc with an internal impedance of 40 k typical. 3. v cc 2.4v 4. v cc < 2.4v 5. measured with outputs open and all inputs at v cc or ground. 6. t r = 5 s 7. noise immunity - pulses < 2 s at v cctp minimum will not cause a reset. downloaded from: http:///
ds1707/ds1708 9 of 10 part marking codes cccccc cccccc ###xx 8-pin dip (300 mil) 8-pin soic (150 mil) 8-pin sop (118 mil) ds170ab yywwrv ###xx ds170ab yywwrv ###xx 170ab ywwrv brand codes code description values ab device type and tolerance 7_, 8_, 8r, 8s, 8t (where_ is a blank) yww or yyww date code. identifies the year and work week the device was assembled. y, the last digit of the year. yy, the last two digits of the year. ww, the work week (values 01 through 52). rv die revision a letter followed by a number (eg. b1) ###xx lot code three numbers followed by 2 letters cccccc country of assembly abbreviation of country name. downloaded from: http:///
ds1707/ds1708 10 of 10 ordering information ordering number package operating temperature version ds1707epa 8-pin dip (300mil) -40c to +85c 5v-5% monitor, /rst, rst ds1707esa 8-pin soic (150 mil) -40c to +85c 5v-5% monitor, /rst, rst ds1707eua 8-pin sop (118 mil) -40c to +85c 5v-5% monitor, /rst, rst ds1708epa 8-pin dip (300mil) -40c to +85c 5v-10% monitor, /rst, rst ds1708esa 8-pin soic (150 mil) -40c to +85c 5v-10% monitor, /rst, rst ds1708eua 8-pin sop (118 mil) -40c to +85c 5v-10% monitor, /rst, rst ds1708repa 8-pin dip (300mil) -40c to +85c 3.3v-20% monitor, /rst, rst ds1708resa 8-pin soic (150 mil) -40c to +85c 3.3v-20% monitor, /rst, rst ds1708reua 8-pin sop (118 mil) -40c to +85c 3.3v-20% monitor, /rst, rst ds1708sepa 8-pin dip (300mil) -40c to +85c 3.3v-10% monitor, /rst, rst ds1708sesa 8-pin soic (150 mil) -40c to +85c 3.3v-10% monitor, /rst, rst ds1708seua 8-pin sop (118 mil) -40c to +85c 3.3v-10% monitor, /rst, rst ds1708tepa 8-pin dip (300mil) -40c to +85c 3.3v-5% monitor, /rst, rst ds1708tesa 8-pin soic (150 mil) -40c to +85c 3.3v-5% monitor, /rst, rst DS1708TEUA 8-pin sop (118 mil) -40c to +85c 3.3v-5% monitor, /rst, rst *contact factory for availability of pb-free versions. e = -40c to +85c temperature range a = 8 lead device p = plastic dip (300 mil) s = soic (150 mil) u = sop (118 mil) downloaded from: http:///
|
